1. Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to various methods of patterning line-type features using a stitched, multiple patterned cut mask that enables the use of tighter contact enclosure spacing rules.
2. Description of the Related Art
Photolithography is one of the basic processes used in manufacturing integrated circuit products. At a very high level, photolithography involves: (1) forming a layer of light or radiation-sensitive material, such as photoresist, above a layer of material or a substrate; (2) selectively exposing the radiation-sensitive material to a light generated by a light source (such as a DUV or EUV source) to transfer a pattern defined by a mask or reticle (interchangeable terms as used herein) to the radiation-sensitive material; and (3) developing the exposed layer of radiation-sensitive material to define a patterned mask layer. Various process operations, such as etching or ion implantation processes, may then be performed on the underlying layer of material or substrate through the patterned mask layer.
Of course, the ultimate goal in integrated circuit fabrication is to faithfully reproduce the original circuit design on the integrated circuit product. Historically, the feature sizes and pitches (spacing between features) employed in integrated circuit products were such that a desired pattern could be formed using a single patterned photoresist masking layer. However, in recent years, device dimensions and pitches have been reduced to the point where existing photolithography tools, e.g., 193 nm wavelength immersion photolithography tools, cannot form a single patterned mask layer with all of the features of the overall target pattern. Accordingly, device designers have resorted to techniques that involve performing multiple exposures to define a single target pattern in a layer of material, which are often referred to as multiple patterning methods or techniques. There are various multiple patterning techniques. One such multiple patterning technique consists of initially forming continuous one dimensional line patterns and thereafter using a cut mask to cut the lines and to form the line ends. The continuous one dimensional line patterns can be formed by various patterning methods, such as EUV lithography, self-aligned double patterning (SADP), self-aligned quadruple patterning (SAQP) or directed self-assembly (DSA). As the overall chip layout continues to shrink as technology advances, two cut masks or a double patterning cut mask may be required to cut the lines so as to form a very dense layout. One common issue that occurs when trying to use a cut mask is that the inner corner rounding of non-rectangular features in a cut mask necessitate a large contact enclosure distance for the associated contact, which has negative impact on chip shrinkage. Therefore, there is a need for a solution of reducing the usage of large contact enclosure spacing rules and increasing the usage of tight contact enclosure spacing rules.
In the design of an integrated circuit product, an overall target pattern or design layout is created for the integrated circuit product. This design layout reflects the location of where various features will be formed in and above a semiconductor substrate, e.g., transistor structures, contact structures, metallization layers, etc. To fabricate the device, the substrate and various layers of material are patterned (or cut) to produce the desired features of the integrated circuit product. Additionally, during these process operations, trenches or openings may be formed in the substrate or one or more layers of material and thereafter filled with another material so as to define a desired feature of the product, such as a metal line that is formed in a previously-formed trench in a layer of insulating material. In general, this process proceeds layer by layer (starting with the substrate itself) until all of the features of the integrated circuit are formed.
FIG. 1A is an example of a portion of an overall target pattern 10 for a portion of the circuit layout for an integrated circuit product. In this example, the overall target pattern 10 is comprised of a plurality of line-type features 12, such as gate structures, metal lines, etc. In general, and as described more fully below, the overall target pattern 10 is created by initially forming continuous line-type features 12 across the substrate and thereafter patterning or cutting the line-type features 12 in the regions indicated in dashed-line areas 13 so as to physically separate the continuous line-type features 12 into the desired structures, i.e., separate gate structures or separate metal lines, etc.
FIG. 1B depicts the product at a point in time where the continuous line-type features 12 have been formed above the substrate. As noted above, the line-type features 12 may be formed using traditional single-mask patterning techniques or multiple mask patterning techniques, such as double patterning, or EUV lithography, or directed self-assembly (DSA), etc. To arrive at the overall target pattern 10 depicted in FIG. 1A, the continuous line-type features 12 must be patterned or “cut” using a so-called “cut mask.” In the case where the overall cut mask must be formed using double patterning techniques, this is accomplished by, among other things, forming two separate “cut masks,” i.e., two separate patterned layers of photoresist material having openings therein. The two cut masks are sequentially formed above the continuous line-type features 12 which are patterned separately through each of the two cut masks. The combination of the openings in each of the first and second cut masks is intended to remove the desired portions of the continuous line-type features 12, i.e., the portions within the dashed-line regions 13 shown in FIG. 1A, so as to arrive at the desired overall target pattern 10 shown in FIG. 1A.
As noted above, the overall cut mask that is required to achieve the overall target pattern 10 is such that it cannot be printed using a single mask with available photolithography tools. Thus, in this illustrative example, the overall target pattern 15 for the overall cut mask is formed using two separate cut masks 15A, 15B. The cut mask 15B is depicted in FIG. 1C using dashed lines in an effort to distinguish it from the cut mask 15A, which is depicted with solid lines in FIG. 1C. Of course, as will be appreciated by those skilled in the art, only the openings 14, 16 of the cut masks 15A, 15B are depicted in FIG. 1C. FIG. 1E depicts the cut mask 15A while FIG. 1F depicts the cut mask 15B. The opening 14 is a non-rectangular opening, i.e., an L-shaped opening, while the opening 16 is a rectangular-shaped opening. As depicted, the cut mask 15A will be covering all portions of the continuous line-type features 12 that are not exposed by the non-rectangular opening 14 in the cut mask 15A. The cut mask 15B will be covering all portions of the continuous line-type features 12 that are not exposed by the rectangular-shaped opening 16 in the cut mask 15B. Accordingly, the overall target pattern 15 for the cut mask is decomposed into a first sub-target pattern (comprised of the non-rectangular opening feature 14), and a second sub-target pattern (comprised of the rectangular-shaped opening feature 16). The terminology “sub-target patterns” is used because each of the sub-target patterns contains less than all of the features in the overall target pattern 15 for the overall cut mask. The features that are incorporated in the sub-target patterns are selected and spaced such that the patterns in each of the sub-target patterns may be readily formed in a single masking layer using available photolithography tools. Ultimately, when the mask design process is completed, data corresponding to the first and second sub-target patterns (modified as necessary during the design process) will be provided to a mask manufacturer that will produce tangible masks corresponding to the sub-target patterns to be used in a photolithography tool to generate the first and second cuts masks 15A, 15B to manufacture the integrated circuit product.
With reference to FIGS. 1C and 1F, the rectangular-shaped opening 16 in the cut mask 15B is comprised of four “outer corners” 17 that have a convex configuration when viewed from outside of the opening 16. With reference to FIGS. 1C and 1E, the non-rectangular opening 14 in the first cut mask 15A has five “outer corners” 17 and one “inner corner” 22. In contrast to the outer corners 17, the inner corner 22 has a concave configuration when viewed from outside of the non-rectangular opening 14.
With continuing reference to FIG. 1C, also depicted are illustrative contacts 18 (generally referred to with the reference number 18, while specific contacts will have additional designations) that will subsequently be formed above the patterned line-type features 12 once the desired cuts have been made to the continuous line-type features 12. In designing the overall circuit layout, device designers must take great care to insure that the contact-to-line-end spacing 20A between the illustrative contact 18 and the cut end of the line is large enough so that, allowing for necessary processing margins when manufacturing the device, the location of the patterned end of the line-type features 12 is correctly positioned relative to the desired location of the contact 18 so that proper electrical contact can be made to the patterned line after the line-type features 12 have been cut. This minimum contact-to-line-end spacing requirement between the contact 18 and the associated end of the cut line-type feature 12 is sometimes referred to as a contact enclosure spacing rule. The spacing 20B between the contact 18 and the sides of the lines 12 is usually treated the same as the contact-to-line-end spacing 20A since the lines 12 are typically very thin (in terms of width).
The configurations of the cut masks 15A and 15B shown in FIG. 1C may be referred to as “as-drawn” configurations, as that is what is anticipated by the device designer when “drawing” the circuit layout. Unfortunately, when it comes to actually producing a real-world patterned photoresist mask and printing it on a wafer, there is a difference between the as-drawn configurations of the openings 14, 16 and the “as-printed” configurations of the openings 14, 16 in the actual patterned photoresist layers. That is, as shown in FIG. 1D, the as-printed openings 14P, 16P in the first and second cut masks 15A, 15B, respectively, tend to exhibit so-called corner rounding as compared to the as-drawn configuration of the openings 14, 16. This corner rounding is indicated by the reference numbers 17R and 22R in FIG. 1D. The rounding of the outer corners 17 of the openings 14, 16 is less problematic because it typically does not contribute to unacceptable amount of unwanted consumption of the line structures 12. However, corner rounding of the inner corner 22 of the non-rectangular opening 14 can cause several problems. Due to its location, the rounding of the inner corner 22R of the non-rectangular opening 14P may result in increasing the amount of the line-type feature 12 adjacent the contact structure 18X (see FIG. 1D) that is removed. As a result of these differences, a tighter (smaller) contact enclosure spacing rule can be used for the contacts labeled 18Y (i.e., the contacts 18Y can be positioned closer to the nearest cut end of the line) as compared to a looser (larger) contact enclosure spacing rule that must be used for the contact 18X which is positioned adjacent the line to be cut using the non-rectangular opening 14P with the inner corner 22R (i.e., the contacts 18X must be positioned farther away from its nearest end of line due to the unacceptable amount of line end consumption caused by the corner rounding of the inner corner 22 in the cut mask). As a result, there may be insufficient landing area for the contact 18X when it is formed, thereby making accurate alignment more difficult (considering necessary processing margins) and perhaps resulting in a contact structure that operates under conditions not anticipated by the design process. For example, if the contact area between the contact 18X and the underlying line 12 is less than anticipated by the design process, there may be a corresponding increase in electrical resistance, which may degrade device performance or may even result in a non-functioning circuit. One way to resolve the negative aspects of such corner rounding would be to increase the spacing between the end of a cut line 12 and the contact 18X, but such a corrective action would result in undesirable consumption of extremely valuable plot space on the substrate. Given the drive to continually reduce the size of integrated circuit products, there is a need to use every means possible to facilitate the use of increasingly tighter contact enclosure rules so as to help achieve the goal of producing such smaller products.
The present disclosure is directed to various methods of patterning line-type features using a stitched, multiple patterned cut mask that enables the use of tighter contact enclosure spacing rules which may solve or at least reduce one or more of the problems identified above.